Aqua-Soft Forums

G5 Is 90 Nanos! G5 Pbs, Here We Come!

G5 IS 90 NANOs!!!! :lol: :coke party:

PBs G5, here we come!!! :P

G5 PMs will be speed bumped for sure :D

PS Seph, it looks like ur baby won`t be on top much longer :(:P

Here is the data from Apple`s site:

PowerMac G5 Data

quote:

--------------------------------------------------------------------------------

State-of-the-Art Process Technology from IBM

The PowerPC G5 is fabricated in one of IBM’s world-class semiconductor manufacturing

facilities. It uses 130-nanometer circuitry with more than 1130 feet of ultrathin wiring—

nearly 800 times thinner than a human hair.With more than 58 million transistors, a

high-performance, silicon-on-insulator (SOI) process for faster operation, and eight layers

of copper interconnects for improved conductivity, this scalable design contributes to

clock speeds up to 2GHz.

--------------------------------------------------------------------------------

New Xserve G5 Data

quote:

--------------------------------------------------------------------------------

The PowerPC G5 is fabricated in IBM’s new $3 billion, state-of-the-art facility in East

Fishkill, New York. To get electronics so small requires miniaturization breakthroughs,

and IBM’s dedication to scientific research has made these advances possible.With

industry-leading build, assembly, and test technology, IBM uses a 90-nanometer

process to produce the PowerPC G5. More than 58 million silicon-on-insulator (SOI)

transistors and eight layers of copper interconnects enable this new processor to

deliver tremendous performance. The use of these advanced technologies also means

the PowerPC G5 draws less power and produces less heat—allowing Apple to pack

two 64-bit 2GHz processors in a 1U form factor.

--------------------------------------------------------------------------------

#96640

I wonder if the new PBs will have holes in the front, since this is how the Xserve dissipates heat,

design_heatb_010604.jpg

#96644

You know what the 90nm fab process means in the long run, though, don't you?

G5s won't get much faster (i.e. maybe up to 3.0GHz) than they already are, because they can't make the chips any smaller than using a 90nm fab process...

"Why?", I hear you cry?

Because 90nm is the absolute smallest that silicon transistors can go before they start suffering critical levels of gate depletion (they stop acting like a switch and start acting like a capacitor), among other funkiness... <_<

#96660

Good news, good news.

@Stevie; I thought IBM were aiming at 3.6GHz 90nm G5s? I'm definatly not disputing you because your much, much smarter and more knowing than me.. But I'm sure I heard the number 3.6 being mentioned.. :blink:

#96668

Originally posted by Stevie BM@Jan 7 2004, 03:45 PM

You know what the 90nm fab process means in the long run, though, don't you?

G5s won't get much faster (i.e. maybe up to 3.0GHz) than they already are, because they can't make the chips any smaller than using a 90nm fab process...

"Why?", I hear you cry?

Because 90nm is the absolute smallest that silicon transistors can go before they start suffering critical levels of gate depletion (they stop acting like a switch and start acting like a capacitor), among other funkiness...  <_<

i know what ur saying but isn`t IBM aiming for 0.65 with it`s SOI technology?

and intel announced that it had found a material (named K4 or something like that) that has much higher heat tolerance?

anyways i`m not saying that we`ll se PBs G5 next month, but the first step has been made ;)

that`s what matters :)

#96694

Originally posted by Stevie BM@Jan 7 2004, 09:45 AM

You know what the 90nm fab process means in the long run, though, don't you?

G5s won't get much faster (i.e. maybe up to 3.0GHz) than they already are, because they can't make the chips any smaller than using a 90nm fab process...

"Why?", I hear you cry?

Because 90nm is the absolute smallest that silicon transistors can go before they start suffering critical levels of gate depletion (they stop acting like a switch and start acting like a capacitor), among other funkiness...  <_<

Where does your knowledge end Stevie? ;)

#96714

he is the Obie-Van Kenobie of AS. He knows everything ;)

he is da masta ;)

#96762

Originally posted by es.xxi+Jan 7 2004, 03:32 PM-->
QUOTE(es.xxi @ Jan 7 2004, 03:32 PM)
Good news, good news.

@Stevie; I thought IBM were aiming at 3.6GHz 90nm G5s? I'm definatly not disputing you because your much, much smarter and more knowing than me.. But I'm sure I heard the number 3.6 being mentioned..  :blink:

They probably could get up to 3.6GHz, but they'll run somewhere around the 50°C mark, I'll bet, with coolers like the ones on the current G5s. Case in point - Intel have been on a 90nm fab for a while, and, whilst the P4 is not the hottest of chips, it's no Via C3, either.

Originally posted by Unbeliever@Jan 7 2004, 04:46 PM

i know what ur saying but isn`t IBM aiming for 0.65 with it`s SOI technology?

and intel announced that it had found a material (named K4 or something like that) that has much higher heat tolerance?

anyways i`m not saying that we`ll se PBs G5 next month, but the first step has been made ;)

that`s what matters :)

SOI technology? Got a link, Unbeliever? I would assume you're referring to SiO2, the current gate dielectric in transistors.

Alls I know is that 90nm ~= 5 atomic layers in Silicon, at which point you get gate depletion et al. without an incredibly high-K dielectric. Speaking of which... Intel's "K4", as you refer to it, is probably one of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or titanium dioxide (TiO2), with a dielectric constant of greater than 3.9. These would enable the less-than-90nm fab processes to take place, but they're A Bugger™ to make and use (that is, the High-K dielectrics, but so are the fabs to use them).

#96767

:jaw drops on the floor: :blink:

i have found my God and His name is Stevie :bow:

there is nothing you don`t know Sir. i bow to you! :bow:

(and i was talking about SOI2 but compared to Stevies reply... i`m a zero :( )

#96843

FYI: Soy technology

Originally posted by @Jan 7 2004, 05:44 PM

Where does your knowledge end Stevie? ;)

Everybody's knowledge ended here...

:P

#96898

woot, powerbooks G5, i'm never gonna get one, but hell, they'll probably be shiny and pretty to look at.

#96913

Originally posted by Unbeliever@Jan 7 2004, 09:16 PM

:jaw drops on the floor: :blink:

i have found my God and His name is Stevie :bow:

there is nothing you don`t know Sir. i bow to you! :bow:

(and i was talking about SOI2 but compared to Stevies reply... i`m a zero :( )

You're not a zero - this is just one of my "things"...

I take a very active interest in low-level computer architecture (I can program in assembly languages >.-_-

#96914

Originally posted by Stevie BM@Jan 7 2004, 11:12 PM

They probably could get up to 3.6GHz, but they'll run somewhere around the 50°C mark, I'll bet, with coolers like the ones on the current G5s.  Case in point - Intel have been on a 90nm fab for a while, and, whilst the P4 is not the hottest of chips, it's no Via C3, either.

SOI technology?  Got a link, Unbeliever?  I would assume you're referring to SiO2, the current gate dielectric in transistors.

Alls I know is that 90nm ~= 5 atomic layers in Silicon, at which point you get gate depletion et al. without an incredibly high-K dielectric.  Speaking of which...  Intel's "K4", as you refer to it, is probably one of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or titanium dioxide (TiO2), with a dielectric constant of greater than 3.9.  These would enable the less-than-90nm fab processes to take place, but they're A Bugger™ to make and use (that is, the High-K dielectrics, but so are the fabs to use them).

Over there -->

For anyone interested in this:

Intel's page on High-K dielectrics

And if you're really bored:

"Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to High-K" (PDF)

Well stevie, this has probably been your most enlightening post. :rule:

Were not zeros Unbeliever, we're -32.5409 (peter might want to add some Pi into that number ;)) but we get used to it... NOT >.< :shy:

#96925

Originally posted by Seph@Jan 7 2004, 11:06 PM

Well stevie, this has probably been your most enlightening post.  :rule:

Were not zeros Unbeliever, we're -32.5409 (peter might want to add some Pi into that number ;)) but we get used to it... NOT >.<  :shy:

Even moreso than my quantum computing posts, Seph? ;)

I'm glad you found it interesting, guys.

Maybe I should post articles about this sorta thing on TCPU... -_-

#96927

hmm well yeah that was prolly the most interesting conversation i have had over here i must say ;) i will deduct 2 points of my -32.5409 scale of suckyness ;)

#96930